1. Field of the Invention
The invention relates generally to computer processing and, in particular, to an apparatus and method for handling fused multiply add operations.
2. Background Art
To improve floating-point arithmetic processing, most modern processors use a process called the fused-multiply add (FMA) to combine a floating-point multiplication operation and a floating-point addition operation for execution as a single instruction, e.g., (A×B)+C. By performing two operations in a single instruction, the FMA reduces overall execution time and hardware costs. The FMA also provides improved precision because rounding need only be performed after both the multiplication and addition operations are performed at full precision (i.e., there is only one rounding error instead of two). The FMA has set a new trend in processor design, and there is a strong desire to optimize efficiency and performance in FMA architectures.
FIG. 1 shows a general schematic of a conventional FMA architecture for implementing FMA operations. First, a multiplier multiplies the A and B operands and outputs the product in carry-save format, while an aligner aligns the C operand based on the exponent difference of A, B, and C. Then, a 3:2 carry-save adder (CSA), an incrementer, and a carry-propagate adder (CPA) combine the aligned C and the product of A and B to produce an intermediate sum, which a complementer complements as necessary, and a leading zero anticipator (LZA) determines the normalization shift amount. Finally, a normalizer and a rounder normalizes and rounds the result to obtain the final mantissa of the FMA operation. Rounding is performed because the result of floating point operations must conform to a particular data format having a finite number of bits.
The adder output may be either positive or negative. Thus, according to conventional FMA architectures, the adder output goes through a complementer to ensure that a negative output is complemented before the output is normalized and a sticky bit is generated.